Test R+dmb.st+rfi-addr-ctrl-[fr-rf]

AArch64 R+dmb.st+rfi-addr-ctrl-[fr-rf]
"DMB.STdWW Wse Rfi DpAddrdR DpCtrldR FrLeave RfBack Fre"
Cycle=Rfi DpAddrdR DpCtrldR FrLeave RfBack Fre DMB.STdWW Wse
Relax=
Safe=Rfi Fre Wse DMB.STdWW DpAddrdR DpCtrldR [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Ws Fr Rf
Orig=DMB.STdWW Wse Rfi DpAddrdR DpCtrldR FrLeave RfBack Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X5=z; 1:X7=x;
2:X1=x;
}
 P0          | P1                  | P2          ;
 MOV W0,#2   | MOV W0,#2           | MOV W0,#1   ;
 STR W0,[X1] | STR W0,[X1]         | STR W0,[X1] ;
 DMB ST      | LDR W2,[X1]         |             ;
 MOV W2,#1   | EOR W3,W2,W2        |             ;
 STR W2,[X3] | LDR W4,[X5,W3,SXTW] |             ;
             | CBNZ W4,LC00        |             ;
             | LC00:               |             ;
             | LDR W6,[X7]         |             ;
             | LDR W8,[X7]         |             ;
Observed
    y=2; x=2; 1:X8=0; 1:X6=2; 1:X2=2;
and y=1; x=2; 1:X8=0; 1:X6=2; 1:X2=2;
and y=2; x=1; 1:X8=0; 1:X6=2; 1:X2=2;
and y=1; x=1; 1:X8=0; 1:X6=2; 1:X2=2;
and y=2; x=2; 1:X8=0; 1:X6=1; 1:X2=2;
and y=1; x=2; 1:X8=0; 1:X6=1; 1:X2=2;
and y=2; x=1; 1:X8=0; 1:X6=1; 1:X2=2;
and y=1; x=1; 1:X8=0; 1:X6=1; 1:X2=2;